In many applications a need exists for clock signals with a symmetrical output, i.e., 50% duty cycle. In particular, it is advantageous in an electronic system to have an output that has a 50% duty cycle. The symmetrical output allows many circuits to operate at peak efficiency and avoid the issue of non-symmetrical and possibly overlapping signals.
In the field of Liquid Crystal Displays (LCDs), for example, a symmetrical signal driving the display is desired because any deviation from a 50% duty cycle results in a DC bias. This DC bias may be detrimental to the long term stability of the LCD. Thus, a driver having a 50% duty cycle can be quite beneficial.
In Voltage Controlled Oscillators (VCOs), it may be desirable to have a symmetrical output to drive circuitry, while at the same time running the VCO at the lowest possible frequency while obtaining a symmetrical output. In a Phase Lock Loop (PLL) a symmetrical output signal is desired in order to more effectively track and correct frequency and/or phase changes. One current approach to achieve the symmetrical output is centered around comparison of differential signals.
For example, in an Integrated Circuit (IC) application, a VCO may be implemented in a fully differential fashion to improve power supply rejection and noise immunity, and the VCO output signal is a distorted differential wave. A circuit may then be used to convert this signal into a square wave. One such approach is illustrated in FIG. 1, where the output signals 104 & 106 from a VCO 100 are coupled to the inputs of a comparator 102 and the output is a square wave. It is very difficult to cause the output to have a 50% duty cycle, because of the difference in the propagation delays from the comparator inputs to output. FIG. 2 shows an example of a comparator. A signal presented on input Inp 220 travels through transistor M1 and transistor M5 before reaching the output. On the other hand, a signal presented on input Inn 222 travels through transistor M2, transistor M3, and transistor M5 before reaching the output. Because of the differences in the paths through the comparator for each input, the input to output delay is different for each input signal. At high frequency, this delay difference may become significant. As a result of the delay difference, the generation of a symmetrical output signal may become very difficult.
Another approach to achieve a symmetrical output is to route a signal to a divide-by-two circuit. Such a circuit produces a symmetrical output. A disadvantage of this approach is that it may not be practical to run a circuit at twice the desired output frequency. Additionally, running a circuit at twice the desired output frequency tends to draw more power, thereby lowering efficiency, generating more heat, and thus lowering the life of components and circuitry.
Therefore, it is desirable to provide a symmetrical output signal with a 50% duty cycle without the need to run the input signal at twice the desired output frequency.